Field of the Invention
The present invention relates generally to dynamically reconfigurable hardware and computing systems and, more particularly to a system and method for developing and executing computing processes using dynamically relocatable hardware objects.
Statement of the Prior Art
Users and developers of computer systems and other processing equipment face three challenges in today's competitive environment: an ever increasing demand for computing power; a need for faster time to market; and a greater demand for operational flexibility.
The development and execution of processing algorithms according to the prior art can be classified under two broad categories of implementation: software and hardware. An algorithm implemented in software utilizes a set of general purpose instructions that provide a high degree of flexibility in implementing a wide variety of processing tasks. However, the processor in such software implementations has a fixed architecture, and the overhead associated with supporting its large number of general purpose instructions decreases overall performance. An algorithm implemented in hardware, on the other hand, such as an application specific integrated circuit (ASIC), is optimized for a single (or a limited number of) processing task(s) and is dedicated to those tasks. Such hardware implementations, however, can provide a higher performance solution but have the disadvantages of lower flexibility and longer time to market.
Traditional software implementations provide many advantages to the developer including reusable processing platforms that can perform many tasks and an iterative design approach. However, these advantages come at the expense of performance. Such traditional software implementations work on an instruction basis which limits throughput. Moreover, they suffer due to their very limited form of parallelism, a lack of dynamic reconfigurability. Microprocessor architectures used with such software implementations are not well suited for efficiently dealing with many applications that require concurrent processing, such as multimedia data and processing network protocols.
Traditional hardware implementations are optimized to provide efficient processing of a single (or a limited number of) algorithm(s). This provides a high level of performance, but since the hardware is fixed, there is limited reuse of the processing platform and the development platform does not allow for iterative development because changes to the hardware are costly and time consuming.
Since the early 1980's, field programmable gate arrays (FPGAs) have been used to provide a partial solution to the limitations encountered in traditional software and hardware implementations. FPGAs are computing devices that can implement virtually any digital circuit in hardware. In addition, many of them can be reconfigured simply by loading them with a different "hardware program." This allows them to implement many processing algorithms with performance that approaches that of dedicated hardware while retaining the flexibility to dynamically reconfigure the implementation when necessary. This hybrid technology of reprogrammable hardware can provide many of the advantages of both hardware and software. Illustrative of such reconfigurable hardware according to the prior art are the methods and apparatus for emulating a circuit design disclosed in U.S. Pat. Nos. 5,109,353 and 5,477,475.
The system and methods according to such prior art are suitable for physical emulation of electronic circuits or systems and use programmable gate arrays including a network of internal probing interconnections of unused circuit paths in the programmable gate arrays.
However, FPGAs alone have several disadvantages which have kept them from enjoying the widespread application to general purpose computing that is their potential. It is only recently that FPGAs have contained enough logic gates to implement complex algorithms. In addition, FPGAs that boast fast runtime reconfiguration, partial reconfiguration, on-the-fly reprogrammability, and the ability to read the internal state of the device (features that are essential to dynamically reconfigurable computing applications), are just moving to full production. The advent of FPGAs which are optimized for reconfigurable computing provides the foundation for reconfigurable applications.
The use of reconfigurable hardware with appropriate development tools and runtime environments to create reconfigurable computing processes will address the performance issues of software approaches while providing the flexibility missing from hardware approaches. The actual processing algorithms are implemented in hardware and have performance commensurate with this approach. Time to market is reduced by allowing an iterative design approach previously unavailable to hardware designers. This gives rise to an ability to update the system in the field which helps to hold off obsolescence. New functionality can thus be implemented in already deployed equipment.
The prior art, however, does not fully realize this potential. Performance for many applications is excellent but the development process is more akin to ASIC development than software development. Furthermore, in current implementations, the reconfigurable hardware is fixed after the development and debug phases in terms of product life cycle, ignoring dynamic field reprogrammability, which is one of the primary advantages of reconfigurable hardware. Finally, current implementations do not take advantage of the parallelism (i.e., the ability to temporally share the hardware resources) to optimize the processing hardware for the tasks at hand.
What is necessary is a method to dynamically change the hardware implementation during execution based on processing requirements. This will provide performance approaching that of custom hardware solutions with the flexibility to adapt to real-time requirements. In addition, the development of the hardware implementations should be provided using traditional software design methodologies to allow a rapid iterative development approach.